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BIOS BASICS
The Basic Input/Output System runs
things from the motherboard..

Andy's Hardware Basics
Strange settings you might see and what they mean...

[See here for details of Award BIOS settings]

BIOS & BOOTING

The Identity Crisis: On initial power-up: The processor in a computer system is completely oblivious to its intended operating environment. However, a design feature of the processor is that it will immediately instigate a routine that will establish the role it has to play and what it has to play with. The processor could just as easily be used in a washing machine or fuel injection system as in a personal computer, something must tell it how to behave.

What the processor calls on to give it this information is a stored program called the BIOS (sometimes referred to incorrectly as the CMOS). BIOS stands for Basic Input Output System. The BIOS program is stored in a non-volatile Read Only Memory chip on the motherboard. Usually an additional memory chip is present which is a battery backed CMOS RAM chip. This chip is used to store the user defined, or variable information.

Newer versions of BIOS chips are now being used, called "Flash BIOS". These chips are non-volatile without using a backup battery, but can be erased and reprogrammed. The advantage being that you can now update the BIOS to take into account changes in technology and to fix major mistakes when the BIOS program was first written.

The Awakening: The first action of the BIOS program is to conduct a "Power On Self Test" (POST for short.) It will check for the presence of items and resources it knows should be there and make sure they are working as expected. Error codes are generated if a fault is found. If the P.O.S.T is completed successfully, the next action is to seek out and configure attached devices. It will then seek out an operating system on a specified drive and initiate that. The BIOS program installs itself into an area of memory and remains there while the computer is running. The BIOS will now process requests by the operating system for information and resources controlled by it .

The process of starting up the routines that kick your computer into life is called "BOOTING". The processor initially "Jumps" to the address of the BOOT BLOCK of the BIOS program i.e. the starting point of that program, and executes that code. When the BIOS has finished its tasks, it will look on the target drive for the BOOT BLOCK of the operating system. This information is held in a special area on a drive known as the MASTER BOOT RECORD or MBR for short. This area is set up by the operating system when it is installed on the drive.

Error Messages: When the BIOS encounters an error, it will generate an error message. These messages can take three different forms depending on when they occur. If the error occurs in the latter stages of the process, a text message may appear on the screen. If the error occurs before the graphics card is initialised, this would be useless. In this case the BIOS generates an audible beep code to indicate that certain fault conditions exist. The third type of error message is a hexadecimal code sent to the 8 bit ISA slots. A special card is required to display this code. This is the only way the BIOS can communicate when an error occurs before the processor is fully initialised or a crucial resource has failed.



Large Block Addressing

The BIOS disk interface (interrupt 13h) is limited to 63 sectors per track (each of 512 bytes) and 1,024 cylinders per drive; while IDE drives can only have 16 heads. Simple calculation gives: 63 x 512 x 1024 x 16 = 528,482,304 bytes. So it is IDE and the BIOS in combination which gives the 528 MB limitation. LBA is an algorithm for transferring the HDD type settings to another type of setting that can be recognised by both the HDD and DOS in order to break the barrier of 528MB that DOS can support. Both the HDD and IDE card / Motherboard must possess this feature for high capacity drives to be utilised.

Pipeline Caches

Pipelining is a method of fetching and decoding instructions in which, several program instructions are in various stages of being fetched or decoded. Ideally, pipelining speeds execution time by ensuring that the microprocessor does not have to wait for instructions; when it completes execution of one instruction, the next is ready and waiting.

Refreshing Dram

Binary information held in dynamic ram decays if it is not constantly rewritten, this process is called "Refreshing". Normal Refresh implementation places the CPU on hold (usually every 15us) while a refresh cycle takes place to the DRAM memory. "Hidden Refresh" is used to increase the CPU bandwidth by not having to put the CPU on hold to refresh the DRAM. The DRAM can be refreshed in the background while the CPU is accessing the internal cache and running the internal instruction giving better performance than normal refresh.

DMA Transfers

This allows a peripheral devices to take control of the memory bus directly. During a DMA cycle, the CPU is idle and has no control of the memory buses. A device with DMA control would take over the buses to manage the transfer directly between the device and the memory. When a peripheral device sends a DMA request, the DMA controller inform the CPU to relinquish the buses. Thus it sends a DMA acknowledge to the peripheral device. When the peripheral device receives the DMA acknowledge, it puts a word on the data bus for write and receives a word from the data bus for read.



Thus the DMA controls the read or write operations and supplies the address for the memory. The peripheral units can then communicate with the memory through the data bus for direct transfer between the two units while the CPU is momentarily disabled. The DMA cycle will stop and remove it's bus request when the word count register in the DMA controller reaches zero. It also inform the CPU of the termination by means of interrupt.

A DMA controller may have more than one channel. Each channel has a request and acknowledge pair of control signals which are connected to separate peripheral devices. The channels for each I/O device are prioritised so that the highest one is serviced before the one with lower priority.



Put 03.05.02 | Rev 16.01.05 | Refresh for latest | FB